Attend ECEE Seminars with guest Shi-Yu Huang, Feb. 10 and 11

Join the School of Electrical, Computer and Energy Engineering and the ASU Center for Semiconductor Microelectronics for a distinguished seminar with Shi-Yu Huang, professor in electrical engineering at the National Tsing Hua University in Taiwan.

About:
Shi-Yu Huang received his bachelor’s and master’s degrees in electrical engineering from National Taiwan University and his doctoral degree in electrical and computer engineering from the University of California, Santa Barbara. He joined the faculty of the electrical engineering department of National Tsing Hua University in Taiwan in 1999. Huang has published more than 190 refereed technical papers, including 70 journal papers. His research interests broadly cover very-large-scale integration, or VLSI, design, automation and testing, with prior experiences in formal verification, power estimation, fault diagnosis and resilient nanometer static random access memory design. More recently, his research has concentrated on all-digital timing circuit designs, such as all-digital phase-locked loops, all-digital delay-locked loops, time-to-digital converters and their applications to parametric fault testing and reliability enhancement for 3D integrated circuits.

Seminar part one: Built-In Self-Repair for the TSVs and Interconnects in a Multi-Die IC
In this talk, Huang presents the built-in self-repair, or BISR, schemes for the through‐silicon vias, or TSVs, in a 3D dynamic random access memory, or 3D DRAM, and the die-to-die interconnects in a 2.5D integrated circuit. It is known that if a 3D DRAM device could operate at a very high speed, even a small delay fault could cause a failure. Even though numerous prior works have been proposed to perform BISR for faulty TSVs in a 3D DRAM device, they cannot handle sub-100-picosecond small delay faults easily. In this work, we aim to fix this problem with a “progressively shrinking pulse-vanishing test.” Our BISR scheme streamlines the entire test-and-repair process, integrating several techniques, including small-delay-fault detection, on-the-spot diagnosis, test result broadcasting, TSV repair and the final validation. Experimental results show that it can indeed detect and repair a small delay fault that causes a sub-100-picosecond extra delay on a TSV. For a 2.5D integrated circuit, we propose a novel connectivity-agnostic BISR scheme. In our scheme, the design-for-BISR circuit inserted in each functional die except the master die is independent of the die-to-die connectivity so that a non-master die can be repeatedly “reused” in many chiplet integrated circuits while supporting in-the-field repair of faulty interconnects to boost the manufacturing yield and in-the-field reliability.

Seminar part two: Speed Learning Scheme To Mitigate The Silent Data Corruption in a Multi-Core Design
Silent Data Corruption, or SDC, has become a growing threat in large-scale infrastructure such as data centers, where massive fleets of multi-core systems operate under high utilization. As a fundamental element in computing platforms, multi-core system-on-chip, or SoC, architectures are particularly vulnerable to timing-related errors that silently propagate across workloads, especially in long-duration, mission-critical applications. In this work, Huang proposes a speed margining scheme to proactively mitigate SDC in multi-core systems. At the hardware level, Huang introduces an enhanced architecture based on dual modular redundancy, or enhanced DMR, in which each core supports two execution gears: a standard performance gear and a shadow performance gear. This arrangement facilitates the establishment of a safe performance margin with built-in SDC alerting capability. In order to demonstrate the effectiveness of the proposed approach, Huang implemented it on both a AMD Zynq™ 7010 field programmable gate array platform and an application-specific integrated circuit design using the TSMC 90-nanometer process, running seven representative learning programs to emulate diverse system conditions. Experimental results show that the system can effectively detect early timing-related errors in real time and dynamically adjust frequency without interrupting system execution. This significantly reduces the incidence of silent data errors and enables multi-core systems to achieve high performance.

Seminar part one: Built-In Self-Repair for the TSVs and Interconnects in a Multi-Die IC
Tuesday, Feb. 10, 2026
1:30–3 p.m.
Goldwater Center (GWC) 487, Tempe campus [map]

Seminar part two: Speed Learning Scheme To Mitigate The Silent Data Corruption in a Multi-Core Design
Wednesday, Feb. 11, 2026
1:30–3 p.m.
Goldwater Center (GWC) 487, Tempe campus [map]